Daniel M. McCarthy
20Patents
9h-index
24Co-inventors
75Inventor score
Filing activity: Apr 27, 1984 → May 3, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5530804A | Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes | Physics | 126 | Expired |
| US5276836A | Data processing device with common memory connecting mechanism | Physics | 77 | Expired |
| US4928225A | Coherent cache structures and methods | Physics | 71 | Expired |
| US5029070A | Coherent cache structures and methods | Physics | 65 | Expired |
| US5485602A | Integrated circuit having a control signal for identifying coinciding active edges of two clock signals | Physics | 35 | Expired |
| US5761215A | Scan based path delay testing of integrated circuits containing embedded memory elements | Physics | 29 | Expired |
| US5666509A | Data processing system for performing either a precise memory access or an imprecise memory access based upon a logical address value and method thereof | Physics | 28 | Expired |
| US8312253B2 | Data processor device having trace capabilities and method | Physics | 28 | Active |
| US4680702A | Merge control apparatus for a store into cache of a data processing system | Physics | 19 | Expired |
| US7433803B2 | Performance monitor with precise start-stop control | Physics | 8 | Active |
| US6766433B2 | System having user programmable addressing modes and method therefor | Physics | 7 | Expired |
| US10360162B2 | Processing systems and methods for transitioning between privilege states based on an address of a next instruction to be fetched | Physics | 4 | Active |
| US9092647B2 | Programmable direct memory access channels | Physics | 3 | Active |
| US9672164B2 | Methods and systems for transitioning between a user state and a supervisor state based on a next instruction fetch address | Physics | 3 | Active |
| US9489316B2 | Method and device implementing execute-only memory protection | Physics | 0 | Active |
| US10073797B2 | Data processor device supporting selectable exceptions and method thereof | Physics | 0 | Active |
| US9824242B2 | Programmable direct memory access channels | Physics | 0 | Active |
| US10002076B2 | Shared cache protocol for parallel search and replacement | Emerging Cross-Sectional Technologies | 0 | Active |
| US8417924B2 | Data processing device and method of halting exception processing | Physics | 0 | Active |
| US9201848B2 | Floating point matrix multiplication co-processor | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.