Memory using distributed data line loading
US4928268A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1989 |
| Grant date | May 22, 1990 |
| Priority date | — |
| Expiry date | Apr 21, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory which contains a global data line pair and a plurality of loads for the global data line pair distributed thereon. The global data lines run the length of the memory, and are connected to a set of arrays distributed along the global data lines, of which each array provides a voltage on the global data lines when selected. The first load is located above the first array and the last is located below the last array. Other global data line loads are placed between consecutive arrays. In a read mode of operation a pair of loads associated with each array is enabled when a corresponding array is selected. Placement of the loads in this manner decreases an access time considerably.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.