Dual cache RAM for rapid invalidation
US4930106A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1988 |
| Grant date | May 29, 1990 |
| Priority date | — |
| Expiry date | Aug 29, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache buffer for a multiprocessor system utilizes two RAMs to store validity bits. Use of these RAMs greatly reduces chip area required to implement the validity buffer and reduces interconnection foil (printed connectors) and hence propagation time. An initial clear state is written into all of the memory locations of both RAMs. One of the RAMs then becomes the active validity bit RAM and the other a standby. When a fast invalidate command is received, upon an invalidate parity error indication from a memory readout, for example, the standby RAM is switched to the active RAM, and the validity bits of the formerly active RAM are cleared in sequential write cycles after it is switched to a standby state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.