Inventor · Houston, TX, US

John E. Larson

48Patents
21h-index
48Co-inventors
85Inventor score

Filing activity: Aug 29, 1988 → Feb 25, 2016

Most-cited inventions

PatentTitleAreaCited byStatus
US6715116B2 Memory data verify operation Physics 142 Expired
US7010652B2 Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency Physics 116 Expired
US6785785B2 Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrency Physics 114 Expired
US6766469B2 Hot-replace of memory Physics 103 Expired
US6684292B2 Memory module resync Physics 97 Expired
US5721935A Apparatus and method for entering low power mode in a computer system Emerging Cross-Sectional Technologies 94 Expired
US5524235A System for arbitrating access to memory with dynamic priority assignment Physics 91 Expired
US6832340B2 Real-time hardware memory scrubbing Physics 64 Expired
US6275885A System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache Physics 64 Expired
US6854070B2 Hot-upgrade/hot-add memory Physics 56 Expired
US6209067A Computer system controller and method with processor write posting hold off on PCI master memory request Physics 46 Expired
US5634073A System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation Physics 44 Expired
US6247102A Computer system employing memory controller and bridge interface permitting concurrent operation Physics 40 Expired
US6823424B2 Rebuild bus utilization Physics 38 Expired
US7320086B2 Error indication in a raid memory system Physics 31 Expired
US4930106A Dual cache RAM for rapid invalidation Physics 30 Expired
US5778413A Programmable memory controller having two level look-up for memory timing parameter Physics 29 Expired
US5819105A System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device Physics 28 Expired
US6785835B2 Raid memory Physics 26 Expired
US5813038A Memory controller having precharge prediction based on processor and PC bus cycles Physics 24 Expired
US6886048B2 Techniques for processing out-of-order requests in a processor-based system Physics 21 Expired
US7028213B2 Error indication in a raid memory system Physics 20 Expired
US5960459A Memory controller having precharge prediction based on processor and PCI bus cycles Physics 17 Expired
US5974501A Method and apparatus for detecting memory device types Physics 17 Expired
US5938739A Memory controller including write posting queues, bus read control logic, and a data contents counter Physics 16 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.