Reducing power consumption in on-chip memory devices
US4932001A · kind A · utility
8Cited by
1References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 1988 |
| Grant date | Jun 5, 1990 |
| Priority date | — |
| Expiry date | Oct 12, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An on-chip semiconductor memory device in which power consumption is significantly decreased by restricting pre-charging of the bit lines to only those clock cycles for which there is a change in word line address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.