Output circuit for a programmable logic array
US4933577A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1989 |
| Grant date | Jun 12, 1990 |
| Priority date | — |
| Expiry date | Apr 10, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17716
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, and clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.