Circuit and method for adding binary numbers with a difference of one or less
US4933894A · kind A · utility
0Cited by
2References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 24, 1989 |
| Grant date | Jun 12, 1990 |
| Priority date | — |
| Expiry date | May 24, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The subject invention is a circuit and method of providing the sum of first and second n bit binary numbers having a difference of one or less. The method comprises combining the least significant bits of the numbers in a first coincidence gate to provide the least significant bit of the sum, combining the nth and (n-1)st bits of the numbers in a first logic network to provide the most significant bit of the sum, and combining solely the ith and (i-1)st bits of the numbers in an ith logic network to provide the ith bit of the sum, for all values of i where 1<i<n+1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.