Fault tolerant digital data processor with improved bus protocol
US4939643A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1987 |
| Grant date | Jul 3, 1990 |
| Priority date | — |
| Expiry date | Jul 29, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault-tolerant digital data processor includes a peripheral device controller for communicating with one or more peripheral devices over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing information. Each peripheral device includes a device interface for transferring information signals between the associated peripheral device and the peripheral bus. The peripheral device controller includes a strobe element connected with the first and second input/output buses for transmitting thereon duplicative, synchronous and simultaneous strobe signals. These strobe signals define successive timing intervals for information transfers along the peripheral bus. Information transfers are normally effected by the transmission of duplicate information signals synchronously and simultaneously on the first and second input/output buses. A transfer cycle element includes a scanner cycle element to determine an operational state of at least one of the peripheral devices connected to the peripheral bus; a command cycle element for executing a command cycle for controlling operation of an attached peripheral device; a read cycle eleme…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.