Joseph M. Lamb
14Patents
8h-index
10Co-inventors
69Inventor score
Filing activity: Jul 29, 1987 → Oct 31, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5379381A | System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations | Physics | 49 | Expired |
| US5559459A | Clock signal generation arrangement including digital noise reduction circuit for reducing noise in a digital clocking signal | Physics | 40 | Expired |
| US4931922A | Method and apparatus for monitoring peripheral device communications | Physics | 28 | Expired |
| US4974150A | Fault tolerant digital data processor with improved input/output controller | Physics | 26 | Expired |
| US4974144A | Digital data processor with fault-tolerant peripheral interface | Physics | 23 | Expired |
| US4926315A | Digital data processor with fault tolerant peripheral bus communications | Physics | 18 | Expired |
| US4939643A | Fault tolerant digital data processor with improved bus protocol | Physics | 17 | Expired |
| US5257383A | Programmable interrupt priority encoder method and apparatus | Physics | 11 | Expired |
| US9258256B2 | Inverse PCP flow remapping for PFC pause frame generation | Emerging Cross-Sectional Technologies | 1 | Active |
| US9208844B1 | DDR retiming circuit | Physics | 1 | Active |
| US9270488B2 | Reordering PCP flows as they are assigned to virtual channels | Electricity | 1 | Active |
| US9891985B1 | 256-bit parallel parser and checksum circuit with 1-hot state information bus | Electricity | 0 | Active |
| US9264256B2 | Merging PCP flows as they are assigned to a single virtual channel | Electricity | 0 | Active |
| US9515946B2 | High-speed dequeuing of buffer IDS in frame storing system | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.