Floating point normalization and rounding prediction circuit
US4941120A · kind A · utility
48Cited by
7References
4Claims
0Family size
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Key dates
| Filing date | Apr 17, 1989 |
| Grant date | Jul 10, 1990 |
| Priority date | — |
| Expiry date | Apr 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49947
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for enhancing certain floating point arithmetic operations, by examining the initial operands and the exponent and fractional results and predicting when the steps of postnormalization and rounding can be skipped. The fraction result format enables a prediction of normalization and rounding under each of the addition, subtraction and multiplication possibilities, and under each of the various choices of rounding mode which are used in floating point arithmetic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.