Microprocessor with a cache memory in which validity flags for first and second data areas are simultaneously readable
US4942521A · kind A · utility
11Cited by
8References
12Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Nov 13, 1987 |
| Grant date | Jul 17, 1990 |
| Priority date | — |
| Expiry date | Nov 13, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When the access is effected sequentially such as the prefetching of an instruction or the restoration of a register in the stack region, the retrieval is effected simultaneously for the consecutive addresses and the result is stored. When the consecutive addresses are to be accessed, the hit is determined relying upon the result that is stored without effecting the cache memory reference. In the case of mishit, the external memory is readily accessed to shorten the overhead time required for the cache memory reference. Therefore, the access time can be shortened in average.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.