Floating gate memory circuit and apparatus
US4945393A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1989 |
| Grant date | Jul 31, 1990 |
| Priority date | — |
| Expiry date | Dec 7, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/803
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially deplete it, and a graded bandgap injector region between the control gate and the floating gate for controlling the injection of carriers into and out of the potential well. Also described is a three element memory cell, including the memory device and two FETs, which operates from a constant, non-switched supply voltage and two-level control voltages. Arrays of memory devices may also be used to detect light in a variety of applications such as imaging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.