Backside metallization scheme for semiconductor devices
US4946376A · kind A · utility
7Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 6, 1989 |
| Grant date | Aug 7, 1990 |
| Priority date | — |
| Expiry date | Apr 6, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/12819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A backside metalization scheme for semiconductor devices includes a vanadium layer disposed on the backside of a wafer and a silver layer disposed on the vanadium layer. An optional intermediate layer comprising either a mixture of vanadium and silver or nickel may be disposed between the vanadium layer and the silver layer. The vanadium layer exhibits excellent adhesion characteristics on the backside of wafers having a finish at least as fine as a 300 grit equivalency while the silver layer exhibits excellent solderability characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.