Addressing of redundant columns and rows of an integrated circuit memory
US4947375A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1988 |
| Grant date | Aug 7, 1990 |
| Priority date | — |
| Expiry date | Mar 2, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for the addressing of redundant elements of an integrated circuit memory is disclosed. This memory comprises an array of row memory elements and column memory elements, respectively addressable by row addresses and column addresses, at least one battery of fuses to store the address of a faulty element of the memory. The method consists: PA0 for one battery, in associating said battery with a row/column address pair; PA0 in memorizing, through the blowing of certain fuses in the battery after the testing of a memory element, the address either of a column element if the faulty element is a column element or that of a row element if the faulty element is a row element; PA0 and in enabling only the row addresses when the stored address is that of a row element or only the column addresses when the stored address is that of a column element, to address either a row redundant element or a column redundant element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.