EEPROM utilizing single transistor per cell capable of both byte erase and flash erase
US4949309A · kind A · utility
106Cited by
8References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 11, 1988 |
| Grant date | Aug 14, 1990 |
| Priority date | — |
| Expiry date | May 11, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of floating gate transistors is connected so that some of the floating gate transistors within the array can be erased without affecting the state of other floating gate transistors within the array, or in the alternative, the entire array of floating gate transistors can be erased simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.