Method for fabricating a BiCMOS device
US4950616A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 1989 |
| Grant date | Aug 21, 1990 |
| Priority date | — |
| Expiry date | May 17, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/009
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention provides a method for fabricating a semiconductor device comprising the steps of forming buried layers on the silicon substrate; etching an epitaxial layer after said layer is grown up, the step further including the processes of etching selectively the silicon epitaxial layer of well region on which a high speed bipolar transistor is formed to be thin and keeping the silicon epitaxial layer of well region on which nMOS transistor is formed remained the same thickness as grown up; and forming a pMOS transistor, a nMOS transistor and a bipolar transistor. High efficiency and high integration is easily attained in fabricating the high speed bipolar transistor and high performance CMOS transistor on same chip and by reducing the difficulty in processing according to the method of present invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.