Process for making integrated circuit with doped silicon dioxide load elements
US4950620A · kind A · utility
33Cited by
4References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1988 |
| Grant date | Aug 21, 1990 |
| Priority date | — |
| Expiry date | Sep 30, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit which uses vertical current flow through arsenic-implanted oxide films to provide low-current loads. These load elements provide a compact four-transistor SRAM which has very simple fabrication and very low power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.