Isolation of insulated-gate field-effect transistors
US4951117A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 19, 1988 |
| Grant date | Aug 21, 1990 |
| Priority date | — |
| Expiry date | Aug 19, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and a method of fabricating the same wherein a semiconductor substrate of one conductivity type is formed of three laterally arrayed portions by providing two trenches in the substrate and filling them with first and second epitaxial layers of an opposite conductivity type. A buried layer of the opposite conductivity type is formed within the substrate. First and second insulator films are provided on the side walls of both trenches. The first portion of the substrate has a first region of one conductivity type. A second region of the one conductivity type is buried within the substrate. A third region of the opposite conductivity type is interposed in the direction of substrate depth between the first and second insulator films. The portion of the substrate includes a fourth region isolated from the first to third regions by the first insulator film. The third portion of the substrate includes a fifth region of the one conductivity type electrically connected to the second region. The first, second and fourth region work as one and the other of drain and source regions, and the gate of a vertical MOS transistor, respectively, and the fifth region is used for…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.