Patent · US Expired

Circuit configuration and a method of testing storage cells

US4956819A · kind A · utility

15Cited by

5References

9Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Kurt Hoffmann · Taufkirchen, DE
Hans-Dieter Oberle · Puchheim, DE
Rainer Kraus · Hersbruck, DE
Oskar Kowarik · Grafing, DE

Key dates

Filing date	Mar 16, 1988
Grant date	Sep 11, 1990
Priority date	—
Expiry date	Mar 16, 2008

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/0963
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A circuit configuration and method for testing storage cells of an integrated semiconductor memory precharges a pair of external bit lines to mutually complementary logic levels. All of the storage cells of a word line are always read-out in parallel. In a "no fault" situation the pair of external bit lines retains its precharge level, whereas in the case of a fault, the level of the external bit line which is precharged to logical 1 falls. This is recognized by a discriminator circuit and analyzed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.