Process for simultaneously fabricating EEPROM cell and flash EPROM cell
US4957877A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1988 |
| Grant date | Sep 18, 1990 |
| Priority date | — |
| Expiry date | Nov 21, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
Abstract
Improved processing which permits the simultaneous fabrication of block erasable flash EPROM cells and individually erasable EEPROM cells. A polysilicon finger extends from the floating gate of the EEPROM cell over a tunnel oxide region. Doped regions are formed under this finger by implanting dopants in alignment with the finger during the implantation of the source and drain regions for the cells and then driving the dopant under the finger. The arsenic dopant used to form the source and drain regions for the cells is used to form the doped regions along with the phosphorus dopant used for the source region of the flash EPROM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.