Low power three-stage CMOS input buffer with controlled switching
US4958088A · kind A · utility
119Cited by
9References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 19, 1989 |
| Grant date | Sep 18, 1990 |
| Priority date | — |
| Expiry date | Jun 19, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS low power Schmitt type input buffer for a dynamic random access memory (DRAM) circuit. This buffer is further characterized in that a falling edge on the input has better than average noise immunity and has a slightly longer propagation time through the buffer than a rising edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.