Semiconductor integrated circuit device
US4959704A · kind A · utility
15Cited by
0References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 1988 |
| Grant date | Sep 25, 1990 |
| Priority date | — |
| Expiry date | May 25, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layers which extend parallel with each other are set so that noises are canceled in differential sense circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.