Dual byte order computer architecture a functional unit for handling data sets with differnt byte orders
US4959779A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 1988 |
| Grant date | Sep 25, 1990 |
| Priority date | — |
| Expiry date | Nov 28, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CPU or other function unit is disclosed which follows one data ordering scheme internally, and in which incoming and/or outgoing data pass through a data order conversion unit for adapting it to a selectable external data ordering scheme. The means for specifying the external data ordering scheme is accessible from outside the physical package(s) in which the functional unit is housed. The data order conversion unit may comprise a load aligner and/or a store aligner, one or both of which may comprise means for shifting informational units of a smaller size within informational units of a larger size. The shift amount may derive from the low order address bits and may be altered depending on the external data ordering means selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.