Synapse cell employing dual gate transistor structure
US4961002A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1989 |
| Grant date | Oct 2, 1990 |
| Priority date | — |
| Expiry date | Oct 11, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synapse cell for providing a weighted connection between an input voltage line and an output summing line having an associated capacitance. Connection between input and output lines in the associative network is made using a dual-gate transistor. The transistor has a floating gate member for storing electrical charge, a pair of control gates coupled to a pair of input lines, and a drain coupled to an output summing line. The floating gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a binary voltage pulse having a certain duration is applied to either one or both of the control gates of the transistor, a current is generated. This current acts to discharge the capacitance associated with the output summing line. Furthermore, by employing a dual-gate structure, programming disturbance of neighboring devices in the network is practically eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.