Apparatus and method for extending a parallel synchronous data and message bus
US4961140A · kind A · utility
35Cited by
13References
13Claims
0Family size
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Key dates
| Filing date | Jun 29, 1988 |
| Grant date | Oct 2, 1990 |
| Priority date | — |
| Expiry date | Jun 29, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input/output bus for a data processing system which has extended addressing capabilities and a variable length handshake which accommodates the difference delays associated with various sets of logic and a two part address field which allows a bus unit and channel to be identified. The various units can disconnect from the bus during internal processing to free the bus for other activity. The unit removes the busy signal prior to dropping the data lines to allow a bus arbitration sequence to occur without slowing down the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.