David Shippy
52Patents
16h-index
53Co-inventors
87Inventor score
Filing activity: Jun 24, 1988 → Oct 8, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4953081A | Least recently used arbiter with programmable high priority mode and performance monitor | Physics | 69 | Expired |
| US4943984A | Data processing system parallel data bus having a single oscillator clocking apparatus | Physics | 65 | Expired |
| US6336183B1 | System and method for executing store instructions | Physics | 56 | Expired |
| US6237081A | Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor | Physics | 53 | Expired |
| US6226722A | Integrated level two cache and controller with multiple ports, L1 bypass and concurrent accessing | Physics | 51 | Expired |
| US5822758A | Method and system for high performance dynamic and user programmable cache arbitration | Physics | 49 | Expired |
| US5822755A | Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache | Physics | 40 | Expired |
| US6061780A | Execution unit chaining for single cycle extract instruction having one serial shift left and one serial shift right execution units | Physics | 38 | Expired |
| US6349382B1 | System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order | Physics | 36 | Expired |
| US4961140A | Apparatus and method for extending a parallel synchronous data and message bus | Physics | 35 | Expired |
| US6336168B1 | System and method for merging multiple outstanding load miss instructions | Physics | 30 | Expired |
| US6543002B1 | Recovery from hang condition in a microprocessor | Physics | 29 | Expired |
| US6820143B2 | On-chip data transfer in multi-processor system | Physics | 25 | Expired |
| US6981072B2 | Memory management in multiprocessor system | Physics | 23 | Expired |
| US7350056B2 | Method and apparatus for issuing instructions from an issue queue in an information handling system | Physics | 23 | Expired |
| US5210828A | Multiprocessing system with interprocessor communications facility | Physics | 20 | Expired |
| US6654876B1 | System for rejecting and reissuing instructions after a variable delay time period | Physics | 16 | Expired |
| US7093080B2 | Method and apparatus for coherent memory structure of heterogeneous processor systems | Physics | 15 | Expired |
| US4974147A | Programmable quiesce apparatus for retry, recovery and debug | Physics | 15 | Expired |
| US7401242B2 | Dynamic power management in a processor design | Emerging Cross-Sectional Technologies | 15 | Active |
| US7313673B2 | Fine grained multi-thread dispatch block mechanism | Physics | 15 | Expired |
| US6957305B2 | Data streaming mechanism in a microprocessor | Physics | 14 | Expired |
| US7103748B2 | Memory management for real-time applications | Physics | 14 | Expired |
| US7490224B2 | Time-of-life counter design for handling instruction flushes from a queue | Physics | 11 | Active |
| US6298436A | Method and system for performing atomic memory accesses in a processor system | Physics | 7 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.