GaAs FET manufacturing process employing channel confining layers
US4962050A · kind A · utility
8Cited by
5References
3Claims
0Family size
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Key dates
| Filing date | Dec 6, 1988 |
| Grant date | Oct 9, 1990 |
| Priority date | — |
| Expiry date | Dec 6, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/141
Abstract
A high speed GaAs FET is provided by forming a sandwiched GaAs channel between AlGaAs layers and employing an Si implant to provide channel doping for the GaAs channel. The poor activation efficiency of Si in AlGaAs relative to its activation efficiency in GaAs provides a channel having a higher active dopant concentration than exists in the adjacent sandwiching layers. This tends to enhance conductivity in the channel relative to the sandwiching layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.