Bus data transmission verification system
US4962501A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 1988 |
| Grant date | Oct 9, 1990 |
| Priority date | — |
| Expiry date | Sep 13, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of transmitting and receiving elements are coupled between read and write buses. The communication paths which connects the tranmitting and receiving elements to the buses are each provided with a fault indicating circuit in series therewith. Each of said fault indicating circuits have logic gating means which include a bit register for each of the bits of a data byte and a parity bit. The output of the bit register means are coupled to isolation drivers which in turn are connected to parity checking circuits and the buses for indicating errors which occur in the bytes of a data word without degrading or delaying data transmission to and from said read and write buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.