Method of making oxide-isolated source/drain transistor
US4963502A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1989 |
| Grant date | Oct 16, 1990 |
| Priority date | — |
| Expiry date | Oct 3, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 are formed by using a silicon etch to form a recess, lining the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusions 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.