Semiconductor memory device having a back-bias voltage generator
US4964082A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1988 |
| Grant date | Oct 16, 1990 |
| Priority date | — |
| Expiry date | Sep 27, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In typical MOS integrated circuit devices, the level of the back-bias voltage which is generated by a built-in back-bias generation circuit and is supplied to a semiconductor substrate is changed by an undesirable leakage current flowing through the semiconductor substrate. The leakage current is not constant. Instead, it becomes relatively small when a main circuit formed on the semiconductor substrate such as a dynamic RAM is not operative, and relatively great when such a circuit is operative. To reduce the change of the back-bias voltage resulting from the change of the leakage current, a back-bias voltage generation circuit is provided which has output capacity of a plurality of levels. Its output capacity is increased in response to an operation control signal of the main circuit. The level change of the back-bias voltage generation circuit can further be reduced by providing a level detection circuit for detecting the level change and a feedback circuit for controlling the back-bias voltage generation circuit in accordance with the output of the level detection circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.