Non-address transition detection memory with improved access time
US4964083A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1989 |
| Grant date | Oct 16, 1990 |
| Priority date | — |
| Expiry date | Apr 27, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory which senses output signals from a selected memory cell during a read cycle using a non-address transition detection apparatus. The memory has a plurality of memory cells which provide signals to a pair of bit lines when selected. An input circuit drives word lines and select a bit line pair of a memory cell located at the intersection of a selected word line and a selected bit line pair. The memory cell outputs bit line signals which are sensed by a combination of a differential amplifier, a level shifter, and a transconductance amplifier, and are thereafter output and presented externally at a logic state representative of a differential current at outputs of the transconductance amplifier. The combination sensing apparatus and a method for constructing such an apparatus decrease access time significantly over a prior art memory using address transition detection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.