Associative memory having simplified memory cell circuitry
US4965767A · kind A · utility
51Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1989 |
| Grant date | Oct 23, 1990 |
| Priority date | — |
| Expiry date | Jul 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell circuit of an associative memory composed of only four NMOS transistors is disclosed. Each memory cells of the circuit is connected two bit lines, a word line, a match setup line for commanding coincidence detection, and a match line for transferring the results of detection. The data signals are stored in the gate capacity of each of the transistors 3. This simplified memory cell circuit contributes to higher integration of the associative memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.