Combinational static CMOS logic circuit
US4968903A · kind A · utility
10Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1989 |
| Grant date | Nov 6, 1990 |
| Priority date | — |
| Expiry date | Aug 3, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A combinational static CMOS logic circuit for providing a plurality of basic two-input logic functions with reduced complexity and integrated circuit area. The combinational static CMOS logic circuit provides either a NAND or an XOR output at a first output terminal and a NOR output at a second output terminal. A configuration input terminal is utilized for selecting between the NAND or the XOR output being provided at the first output terminal. In an alternate configuration, the combinational static CMOS logic circuit provides either a NOR or an XNOR output at a first output terminal and a NAND output at a second output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.