Semiconductor memory device having a timing generator circuit which provides a write pulse signal which has an optional timing relationship with the chip select signal
US4970687A · kind A · utility
14Cited by
4References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1988 |
| Grant date | Nov 13, 1990 |
| Priority date | — |
| Expiry date | Jun 8, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bipolar type RAM having latches which accept and hold address signals, input write data and a write enable signal supplied from outside of the corresponding RAM chip, in accordance with strobe signals, and a timing generator circuit which forms the strobe signals and a write pulse required for a write operation and satisfying predetermined timing conditions, on the basis of a chip select signal supplied from outside.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.