Semiconductor memory device
US4972371A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1988 |
| Grant date | Nov 20, 1990 |
| Priority date | — |
| Expiry date | Jun 7, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.