Digital data processor with fault-tolerant peripheral interface
US4974144A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1989 |
| Grant date | Nov 27, 1990 |
| Priority date | — |
| Expiry date | Jun 16, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault-tolerant digital data processing system comprises a first input-output controller which communicates with at least one peripheral device over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing signals from the input/output controller to the peripheral device. A device interface is coupled to the first and second input/output buses and to an associated peripheral device for transferring information between the buses and the associated peripheral device. In normal operation, the device interface applies duplicate information signals synchronously and simultaneously to the input/output buses for transfer to the input/output controller. The device interface also receives, in the absence of fault, duplicative information signal synchronously and simultaneously from the first and second input/output buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.