Programmable quiesce apparatus for retry, recovery and debug
US4974147A · kind A · utility
15Cited by
5References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1988 |
| Grant date | Nov 27, 1990 |
| Priority date | — |
| Expiry date | Dec 21, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2736
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for suspending processor operation in response to an error indication wherein the processor is cycled to a known state prior to the stopping of the system clock to enable the system to be interrogated in order to determine the cause of the error indication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.