Fault tolerant digital data processor with improved input/output controller
US4974150A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1989 |
| Grant date | Nov 27, 1990 |
| Priority date | — |
| Expiry date | Jun 16, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals. The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.