High density DRAM
US4977436A · kind A · utility
20Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1988 |
| Grant date | Dec 11, 1990 |
| Priority date | — |
| Expiry date | Jul 25, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
Abstract
A high density DRAM having a plurality of cells each including a storage capacitor and a single control FET formed together in a trench to substantially reduce planar area of the cell. The FET drain is formed in the upper portion of a pedestal and is accessible externally through a metal line, which reduces line resistance and capacitance. Field oxide is included to isolate capacitors and reduce leakage and breakdown.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.