Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips
US4978639A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 1989 |
| Grant date | Dec 18, 1990 |
| Priority date | — |
| Expiry date | Jan 10, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Metallized via-holes and a wraparound metal plating are simultaneously formed on semiconductor chips by patterning a photoresist mask on the front surface of the wafer to open windows over metal pads as well as the grid areas where wraparound plating is desired; etching off the exposed metal if necessary and forming via-holes and grooves in the wafer by reactive ion etching to a depth which is less than the total thickness of the wafer; depositing a thin conductive film along the walls of the grooves and via-holes by electroless methods; plating the walls of the grooves and the via-holes with conductive metal by electrolytic methods; removing the back surface of the wafer ("backlapping") along with the floors of both the grooves and the via-holes, to expose the metal on the wall of the via-holes and separate the individual chips; and, depositing conductive metal on the back surface of the individual chips to complete the grounding path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.