Method of producing integrated semiconductor structures comprising field-effect transistors with channel lengths in the submicron range using a three-layer resist system

US4980317A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Otto Koblinger · Ditzingen, DE
• Reinhold Muhl · Altdorf, DE
• Hans-Joachim Trumpp · Stuttgart, DE

Key dates

• Filing date: Mar 21, 1989
• Grant date: Dec 25, 1990
• Expiry date: Mar 21, 2009

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/97
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed is a method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, wherein a three-layer resist system is used to produce a polymer or resist mask. The polymer or resist mask thus produced is used to etch a layer of polysilicon on the semiconductor substrate. The method is characterized in that the pattern, produced conventionally in the top layer of the three-layer resist and including an angle < about 90.degree., is transferred by RIE, using CF.sub.4, to the center layer of plasma nitride and by RIE, using oxygen, to the bottom resist or polymer layer. In a prior art method, this was followed by lateral etching in oxygen to reduce the dimensions of the mask by a desired amount. The improved method of the invention provides for the plasma nitride mask to be removed first, using, if necessary a facetting step in oxygen to increase the positive angle in the mask structure, and then for the latter structure to be laterally etched in oxygen to reduce its dimensions by the desired amount. As the angle in the mask is < about 90.degree., the parameters for lateral etching may be chosen such that the etch process is larg…