Dual triggered edge-sensitive asynchrounous flip-flop
US4980577A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 23, 1989 |
| Grant date | Dec 25, 1990 |
| Priority date | — |
| Expiry date | May 23, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An architecture for bistable circuits with minimized sensitivity to metastability events and with improved operation in signal timing, arbitration, and protocol applications. Conventional edge-triggered flip-flops require input signals to remain present during certain set-up and/or hold time intervals on an input line "data path" for sampling at an instant determined by a separate synchronization input signal. In contrast, the present invention uses two edge-sensitive input lines which are triggered essentially independently without either being synchronized by or depending upon the other. The flip-flops also have twin, independently operable, level sensitive and selected priority PRESET and CLEAR input lines. The active edge or level polarity is programmable for each input line. Alternate embodiments for complementary classes of asynchronous timing perform specific bistable functions, such as set-reset, or toggle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.