Sequential prefetching with deconfirmation
US4980823A · kind A · utility
82Cited by
7References
24Claims
0Family size
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Key dates
| Filing date | Jan 5, 1990 |
| Grant date | Dec 25, 1990 |
| Priority date | — |
| Expiry date | Jan 5, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer memory management method for cache memory uses a deconfirmation technique to provide a simple sequential prefetching algorithm. Access sequentially is predicted based on simple histories. Each memory line in cache memory is associated with a bit in an S-vector, which is called the S-bit for the line. When the S-bit is on, sequentiality is predicted meaning that the sequentially next line is regarded as a good candidate for prefetching, if that line is not already in the cache memory. The key to the operation of the memory management method is the manipulation (turning on and off) the S-bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.