Lishing Liu
16Patents
15h-index
18Co-inventors
67Inventor score
Filing activity: Dec 18, 1987 → Jan 9, 1995
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5265232A | Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data | Physics | 96 | Expired |
| US5418922A | History table for set prediction for accessing a set associative cache | Physics | 95 | Expired |
| US5282274A | Translation of multiple virtual pages upon a TLB miss | Physics | 95 | Expired |
| US4775955A | Cache coherence mechanism based on locking | Physics | 83 | Expired |
| US4980823A | Sequential prefetching with deconfirmation | Physics | 82 | Expired |
| US5604882A | System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data processing system | Physics | 71 | Expired |
| US5148538A | Translation look ahead based cache access | Physics | 68 | Expired |
| US5317716A | Multiple caches using state information indicating if cache line was previously modified and type of access rights granted to assign access rights to cache line | Physics | 57 | Expired |
| US5507028A | History based branch prediction accessed via a history based earlier instruction address | Physics | 46 | Expired |
| US5230070A | Access authorization table for multi-processor caches | Physics | 41 | Expired |
| US5392410A | History table for prediction of virtual address translation for cache access | Physics | 36 | Expired |
| US5130922A | Multiprocessor cache memory system using temporary access states and method for operating such a memory | Physics | 35 | Expired |
| US5018063A | Method for reducing cross-interrogate delays in a multiprocessor system | Physics | 29 | Expired |
| US5210848A | Multi-processor caches with large granularity exclusivity locking | Physics | 28 | Expired |
| US5214766A | Data prefetching based on store information in multi-processor caches | Physics | 23 | Expired |
| US5016168A | Method for storing into non-exclusive cache lines in multiprocessor systems | Physics | 14 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.