Method and apparatus for detecting and correcting errors in a pipelined computer system
US4982402A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1989 |
| Grant date | Jan 1, 1991 |
| Priority date | — |
| Expiry date | Feb 3, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current instruction). Since synchronous errors prevent continued execution of the current instruction, it is preferable that the last stable state conditions of the faulting CPU be restored and the faulting instruction reexecuted. These stable state conditions advantageously occur between the execution of each instruction. However, in a pipelined computer system, it is difficult to identify the beginning and ending of a selected instruction since multiple instructions are in process at the same time. Accordingly, the execution unit is selected to be the point of synchronization between error handling and instruction execution. Once the error is indentified as asynchronous or synchronous and the exe…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.