High performance bipolar differential sense amplifier in a BiCMOS SRAM
US4984196A · kind A · utility
48Cited by
0References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 1988 |
| Grant date | Jan 8, 1991 |
| Priority date | — |
| Expiry date | May 25, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sensing and decoding scheme layout for a memory device comprising an array made up of columns and rows of memory cells is disclosed wherein sense amplifiers and pairs of memory cell columns are positioned so as to collectively fit within the pitches of the memory cells of the memory cell column pairs and where the sense amplifiers are connected in a one-to-one correspondence with columns of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.