Semiconductor memory
US4984212A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 1990 |
| Grant date | Jan 8, 1991 |
| Priority date | — |
| Expiry date | Feb 14, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converted parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of the parallel signal action.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.