Multiplexed serial register architecture for VRAM
US4984214A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1989 |
| Grant date | Jan 8, 1991 |
| Priority date | — |
| Expiry date | Dec 5, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells. A first set of mux devices selects one of the two pairs of folded bit lines from each of the arrays, and a second set of mux devices selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.