Method of assembling stacks of integrated circuit dies
US4984358A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 18, 1990 |
| Grant date | Jan 15, 1991 |
| Priority date | — |
| Expiry date | Jun 18, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49792
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit dies, while still in wafer form, are prepared for stacking without requiring packaging. Holes are made through a wafer having a plurality of integrated circuit dies and are placed between the dies and adjacent the die pads. A layer of insulating material is placed on the wafer and in the outer periphery of the holes. An electrically conductive connection is made between the top of each pad and the inside of the insulating material in an adjacent hole. The insulating layer and the electrically conductive layer can be further extended to the backside of the dies if desired. The dies are separated from each other and can be assembled in a stack and/or surface mounted to a substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.