Molded integrated circuit package incorporating thin decoupling capacitor
US4989117A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 12, 1990 |
| Grant date | Jan 29, 1991 |
| Priority date | — |
| Expiry date | Feb 12, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/916
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A decoupling scheme which is particularly well suited for use with molded integrated circuit packages incorporating lead frames is presented. In accordance with the present invention, a thin decoupling capacitor is used which is comprised of a ceramic or like substrate having printed or otherwise applied thereon conductive layers, dielectric layers (e.g., glass/ceramic dielectric paste or dielectric sol-gel) and protective layers. Mounted on this thin capacitor is an integrated circuit chip. This thin capacitor/IC chip assembly is attached directly to the IC lead frame and thereafter encapsulated within the molded package resulting in a decoupling scheme which is internal to the molded IC package. Printed conductors on the thin capacitor's ceramic substrate are attached to appropriate fingers of the lead frame by welding, soldering or the like to effect strong mechanical and electrical contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.